ESC (Electrostatic Chuck) is a core component in semiconductor manufacturing equipment that uses electrostatic field force to fix wafers. With its characteristics of "no mechanical stress and high-precision temperature control", it replaces traditional mechanical fixtures in key processes such as etching and deposition, and has become an essential component for advanced processes below 7nm. The core of its technology lies in the collaborative design of material properties and electric field regulation.
1、 Working principle and structural innovation
ESC is based on the Coulomb force adsorption principle, which involves embedding metal electrodes (such as molybdenum mesh) on a ceramic substrate. When a direct current voltage of 100-300V is applied, an electrostatic field is formed between the electrodes and the wafer, and adsorption force (usually 0.5-1.0kg/cm ²) is generated using van der Waals force and mirror force. A typical three-layer structure includes:
1. Insulation ceramic layer: made of 99.99% high-purity alumina or aluminum nitride ceramics, with a dielectric strength of>20kV/mm, to prevent high-voltage breakdown;
2. Micro nano electrode layer: A mesh electrode with a line width of 50-100 μ m is formed by laser etching, and the electric field uniformity error is less than 3%;
3. Functional composite layer: A 50nm thick SiN coating is deposited on the surface to reduce particle contamination (>0.1 μ m particle adsorption rate<0.05 particles/cm ²).
2、 Material technology and performance barriers
1. Nano level optimization of ceramic substrates
Aluminum nitride ceramics, with a thermal conductivity of 230W/(m · K), achieve wafer temperature uniformity of ± 0.3 ℃ through backside helium cooling (pressure 80Torr) during etching. Its thermal expansion coefficient (4.5 × 10 ⁻⁶/℃) has a matching error with the silicon wafer of less than 2%, avoiding wafer warping caused by thermal mismatch (<8 μ m).
2. Coordinated regulation of electric and thermal fields
In TSMC's 3nm EUV etching equipment, ESC optimizes the electrode layout through finite element simulation, controls the surface electric field gradient at ± 2%, and uses built-in tungsten resistance wires (power density 5W/cm ²) to achieve stable temperature of 25 ± 0.5 ℃ for 12 inch wafers, ensuring a uniformity of etching depth of ± 0.8%.
3、 Technical challenges in advanced manufacturing processes
1. Ultra thin wafer adaptation: For wafers below 30 μ m, a porous ceramic substrate (porosity of 18%) is used with negative pressure assistance to reduce interface stress to 0.08MPa and prevent cracking;
2. Electrostatic discharge (ESD) protection: In GaN power device manufacturing, graphene conductive network (square resistance<80 Ω/□) is introduced on the surface of ESC to control the peak electrostatic voltage within 30V and avoid breakdown of gate oxide layer.
