Have you ever thought about the fact that the chips at our fingertips are undergoing a silent "dimension revolution"? No longer satisfied with expanding on a flat surface, they are beginning to "stand up" and advance into three-dimensional space. This is not a plot from a science fiction movie, but a real challenge at the forefront of the semiconductor industry, which is also highly capital-intensive.
With the explosive growth of global computing demand driven by artificial intelligence (AI), the limitations of traditional two-dimensional (2D) chip architecture are becoming increasingly apparent. In order to break through the physical bottlenecks of Moore's Law and achieve more powerful performance with lower power consumption, chip designers are starting to focus on volumetric structures. From gate-all-around (GAA) transistors, complementary field-effect transistors (CFET), to 3D storage architectures, the "buildings" of chips are getting taller and more complex.
The "Butterfly Effect" of 0.1 Nanometers: The Billion-Dollar Cost of Data Centers
However, as chips begin to "stand up," they also bring unprecedented manufacturing challenges. In these advanced three-dimensional architectures, the performance of devices increasingly depends on the shape and quality of their vertical structures. You can imagine that if there are slight deviations in the thickness, vertical alignment, or surface smoothness of each wall while constructing a tall building, the structural stability and energy consumption of the entire building would be significantly compromised. For chips, the scale of these deviations is even more minuscule.
Here, the "walls" refer to what we commonly call the sidewalls of the chip. The angles, roughness, and uniformity of these sidewalls directly affect the performance consistency and leakage of 3D chips. At the cutting-edge process nodes, even a mere 0.1 nanometer of systematic deviation in the critical dimensions of transistors could lead to significant reductions in the energy efficiency of chips. Don’t underestimate this 0.1 nanometer; the resultant "butterfly effect" is astounding: a massive data center could end up consuming trillions of terawatt-hours (TWh) more per year due to this, rendering additional electricity costs easily reaching hundreds of millions of dollars! This is a cost that no tech giant can afford to ignore.
Therefore, how to accurately measure and control these microscopic sidewall structures has become a key factor determining the performance of AI chips and the operating costs of data centers.
Breaking Tradition: Nearfield Instruments’ "All-Seeing Eye"
In the past, the industry primarily relied on transmission electron microscopy (TEM) to obtain such fine sidewall information. While TEM can provide extremely high-resolution insights, it is a destructive testing method that requires samples to be removed from the production line for slicing and thinning, which is time-consuming and labor-intensive, and cannot meet high-throughput production demands.
Addressing this pain point, an innovative company named Nearfield Instruments brought a revolutionary solution – they launched the "Sidewall Imaging Mode" and integrated it into their QUADRA high-throughput scanning probe metrology platform. This technology is like equipping chip manufacturing with an "all-seeing eye"!
The most impressive aspect of this technology is that it can non-destructively and inline measure the 3D sidewall profiles of high aspect ratio structures in advanced logic and memory devices. This means chip manufacturers can monitor the quality of the chip's sidewalls in real-time and in bulk on the production line without damaging the product. This patented technology extends the functionality of atomic force microscopy (AFM) by utilizing Nearfield Instruments' unique cantilever design, sensor fusion, and trajectory control technology to simultaneously capture both vertical and lateral interactions, thereby enabling complete 3D reconstruction of complex structures such as etched gates, nanosheets, and deep storage channels. This undoubtedly provides unprecedented data support for statistical process control (SPC) and rapid process optimization.
Energy Efficiency Revolution: The Green Future of AI Chips
The emergence of this technology is not just an advancement in measurement methods; it is also a driving force for a profound revolution in energy efficiency.
- More Accurate Manufacturing Process:By achieving precise control over the third dimension of chips, manufacturers can greatly enhance process accuracy and reduce performance fluctuations caused by structural defects.
- More Energy-Efficient AI Chips:Precise sidewall control means lower leakage and higher transistor efficiency, directly resulting in significant improvements in the energy efficiency of AI chips.
- More Efficient Data Centers:As AI chips become more energy-efficient, the overall energy consumption of data centers will also decrease, saving billions of dollars in electricity costs for large-scale data center operators while significantly reducing carbon emissions and contributing to green computing.
Additionally, this non-destructive inline detection capability can greatly accelerate the innovation cycle of chips, improve manufacturing yield, and allow the next generation of AI chips to reach the market faster and more stably.
Vertical Development: An Inevitable Trend in the Era of 3D Chips
As stated by Dr. Hamed Sadeghian, co-founder and CEO of Nearfield Instruments, “The road to enhancing computing performance for any device is vertical. As devices move fully into the third dimension, process control must keep pace.”
The vertical development of chips is an inevitable trend in the semiconductor industry. From flat to three-dimensional, this "dimensional evolution" is profoundly changing the design, manufacturing, and performance of chips. Innovative technologies like the Sidewall Imaging Mode are key to safeguarding this trend. They allow engineers to truly "see" every detail of the microscopic world, thus creating stronger, more efficient, and more energy-saving AI chips, providing a solid hardware foundation for our leap into an intelligent future. In the era of 3D chips, opportunities are limitless, and challenges and breakthroughs coexist; this technological race has only just begun.
